1. Field of the Invention
This invention relates to semiconductor integration circuit devices, and more particularly, to semiconductor voltage generator circuits.
2. Description of the Related Art
Semiconductor memory devices can, in general, be characterized as either volatile or non-volatile. In volatile memory devices, information can be stored in two ways. First, in devices, such static random access memory (SRAM), information is stored by setting the logical state of a bi-stable flip-flop. Second, in devices, such as dynamic random access memory (DRAM), information is stored by charging a capacitor. In either case, the data is stored and can be read out as long as power is applied; however, the data is lost when the power is turned off.
Non-volatile semiconductor memory devices are capable of storing the data, even with the power turned off. MROM, PROM, EPROM, and EEPROM are examples of such devices. In non-volatile memory devices, data storage may be permanent or re-programmable, depending upon the technology used. Non-volatile memories are frequently used for program and microcode storage in a wide variety of applications such as in avionics, telecommunications, and consumer electronics. Devices such as Non-Volatile SRAM (nvSRAM) combine a single-chip volatile memory and a non-volatile memory. Such devices are sometimes used in systems that require a fast, re-programmable non-volatile memory. In addition, dozens of special memory architectures have evolved which contain additional logic to optimize performance for application-specific tacks.
In non-volatile semiconductor memory devices, since MROM, PROM, and EPROM it is relatively difficult for users to renew memory contents. On the other hand, an EEPROM is electrically erasable and readable. Hence, an EEPROM memory is frequently used in applications that require continuous renewal.
Flash EPROM (hereinafter referred to as “Flash Memory”) is suitable for applications such as for use as a large capacity subsidiary memory device. The reason for this is that the flash memory has a higher integration compared to conventional EEPROM memory. NAND-type flash memories have an even higher integration than NOR flash memories.
In flash memories, if memory cells are programmed once, the programmed memory cell must be erased in order to store new data. That is, flash memories do not support an over-write function. Various methods for programming and erasing flash memories are disclosed in various patents such as in U.S. Pat. No. 6,061,270 entitled in “METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICE WITH PROGRAM DISTURB CONTROL”, U.S. Pat. No. 6,335,881 entitled in “METHOD FOR PROGRAMMING A FLASH MEMORY DEVICE, and U.S. Pat. No. 6,370,062 entitled in “NAND-TYPE FLASH MEMORY DEVICE AND METHOD OF OPERATING THE SAME”.
In order to erase or program memory cells in some non-volatile memory devices, a higher voltage than the power voltage is required (hereinafter referred to as “a high voltage”). An exemplary high voltage generator circuit is disclosed in U.S. Pat. No. 5,642,309 entitled in “AUTO-PROGRAM CIRCUIT IN A NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE”.
FIG. 1 is a schematic block diagram of a prior art high voltage generator circuit. The prior art high voltage generator circuit 10 shown in FIG. 1 includes a charge pump 11, a voltage divider 12, a comparator 13, an oscillator 14, and a clock driver 15. The high voltage Vpgm generated by the charge pump 11 is divided by voltage divider 12. The divided voltage Vdvd is compared with a reference voltage by the comparator 13. The oscillation signal OSC from the oscillator 14 is provided to the charge pump 11 by circuit 15, based on the result of the comparison.
The charge pump 11 generates the voltage Vpgm in response to a clock signal CLK from the clock driver 15. However, the transmission of the CLK to the charge pump 11 is turned on and off according to the result of a comparison between the divided voltage and the reference voltage.
In a control mode, the clock signal CLK is generated until the high voltage Vpgm reaches a target level Vt. Then the charge pump 11 is turned off. There is a delay in turning off the charge pump due to the response speed (time) of the comparator 13. Such a delay is generally inevitable in a high voltage generator circuit employing feedback control methods such as those shown in FIG. 1.
Due to the delay in turning off the clock signal CLK, a ripple phenomenon occurs. That is, the high voltage is not maintained regularly. The reason that the irregular ripple occurs is that the clock signal CLK is not regularly provided to the charge pump 11. This is illustrated in FIG. 2. After the high voltage Vpgm reaches the target voltage Vt, the clock signal CLK is only periodically provided to the charge pump 11. Therefore, as shown in FIG. 2, a ripple of the high voltage Vpgm occurs. In a non-volatile memory device that includes a high voltage generator circuit such as that described above, due to irregular ripples, the threshold voltage profile becomes wide. This is undesirable.